USB 2.0 PHY for SoC Designs | Cadence IP
HSIC USB 2.0 PHY IP
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
Difference between USB and ULPI - Electrical Engineering Stack Exchange
usb3300-ezk hi speed usb host or device phy with ulpi low pin interface
EETimes - New FPGA-based USB 3.0 SuperSpeed Device Controller From SLS
USB 2.0 Full High Speed Solution | NXP Semiconductors
Standalone USB Transceiver Chip - EEWeb
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB 2.0 PHY IP core | Arasan Chip Systems
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
Usb3300 High Speed Usb Host Device Or Otg Phy 2.0 3.3v T/r 32-pin Qfn Ep Ic Chip Usb3300-ezk-tr - Buy Usb3300-ezk-tr,Usb3300,Usb3300 High Speed Usb Host Device Or Otg Phy 2.0 3.3v T/r
USB-IF certified solutions for USB type-C and Power Delivery - STMicroelectronics
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
USB Communicator
XR2280x Hi-Speed USB to 10/100 Ethernet Bridge ICs - MaxLinear | Mouser
USB 3.0 PHY for SoC Designs | Cadence IP
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Mixed-Signal Verification for USB 2.0 Physical Layer IP
TUSB1210 data sheet, product information and support | TI.com
USB3250 | Microchip Technology
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Chip controls up to seven USB-C ports, and Power Delivery
Physical layer - Wikiwand
